不同气体环境下532nm激光诱导硅表面形貌的研究

研究了在不同气体环境下,利用532 nm Nd∶YAG纳秒脉冲激光累积辐照单晶硅表面形成的微结构,结果表明,在其他条件相同,背景气体不同的情况下,背景气体对硅表面形貌的形成起着重要的作用。具体分析了真空、N2和SF6 3种环境气氛下形成的微结构,结果显示,在SF6中形成的锥形微结构的数密度比在N2和真空中的大,并且锥形具有更大的纵横比;在N2、真空和SF6中形成的微结构尺寸依次减小。SF6气氛下,激光辅助化学刻蚀的效率比在真空和N2气氛中的高。另外,辐照区域边缘有波纹微结构形成,分析认为,该微结构的形成是由表面张力波的冷却导致的。     

体结构GaAs光导开关实验研究

 为解决光导开关耐受场强的提高问题,研制了2种体结构光导开关,并进行了实验研究。两种开关均由半绝缘GaAs材料制成,一种尺寸为10.0 mm×10.0 mm×0.6 mm,电极位于10.0 mm×10.0 mm面上相对位置,电极直径6 mm;另一种尺寸为15.0 mm×15.0 mm×3.0 mm,8 mm直径电极位于15.0 mm×15.0 mm面上相对位置。测试了第1种开关在不同半高宽脉冲加载电压下的击穿电压,结果表明其最大耐受电压达7.6 kV,击穿电场127 kV/cm。对第2种结构测试了开关在直流加载条件下的暗态伏安特性并进行了触发实验,结果表明在15 kV工作电压下,其放电最大电流超过3.5 kA。     

激光诱导铝合金E414d等离子体电子温度的空间分布

 采用调Q Nd:YAG脉冲激光诱导铝合金E414d,研究了等离子体的谱线强度、电子温度和电子密度。建立Al (Ⅰ) 256.80 nm、Al (Ⅰ) 308.21 nm和Al (Ⅰ) 396.15 nm的波耳兹曼平面,实验发现距靶面高度1.5 mm处等离子体的电子温度最高。罗仑兹函数拟合Mg (Ⅰ) 285.21 nm得到等离子体的电子密度是1.9×10₁₈ cm_-3,远大于局域热力学平衡所需的电子密度值9.8×10₁₅ cm_-3,证明实验得到的等离子体满足局部热力学平衡。     

水中镉含量的激光诱导击穿光谱高灵敏快速检测

 为了对水中的痕量镉进行高灵敏快速检测,实验采用一种未受污染的薄木片作为基底来吸收水样品,将其晾干后再用激光诱导击穿光谱（LIBS）技术对其进行分析,克服了用LIBS技术直接分析水样品时灵敏度低和稳定性差等问题。实验中选择214.44 nm的镉离子线作为分析线以提高光谱检测的灵敏度,建立了用于定量分析的校正曲线,镉的检出限达到55 μg/L,重复测量的信号相对标准偏差小于5%,单次测量的时间短于5 min。     

高损伤阈值三倍频分离膜

 设计了Nd：YAG激光用三倍频分离膜,膜层材料为SiO₂和HfO₂。经过优化,膜系在355 nm处的反射率在99%以上,在532 nm和1 064 nm处透射率也在99%以上。采用电子束蒸发技术,在熔融石英基底上制备了样品,经测量,制备的分离膜光学性能与设计值接近。分离膜在355 nm激光辐照下的损伤阈值为5.1 J/cm²,并用微分干涉显微镜表征了薄膜损伤形貌。     

一种提高相对论返波管功率容量的方法

 对相对论返波管实验中射频击穿现象进行了分析和数值模拟研究,发现谐振反射器和慢波结构的局部场增强诱导了场致电子发射,引起了金属表面的射频击穿,通过研究分析,提出采用分布反馈式谐振反射器,并采用梯形倒角非均匀慢波结构替换正弦慢波结构的方法来抑制射频击穿。数值模拟研究表明,在微波功率2 GW时,改进后的反射器最大场强由1.4 MV/cm降低为570 kV/cm,慢波结构表面最大电场由1.1 MV/cm降低到780 kV/cm。改进后的结构在二极管电压765 kV时获得了微波功率2.2 GW、脉宽45 ns的实验结果,微波功率和脉宽得到显著提升。     

Novel high-voltage self-adaptive power device based on interface charge＊

This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor （LDMOS） with self- adaptive interface charge （SAC） layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer （EI） and increase breakdown voltage （BV）. The BV and EI of SAC LDMOS increase to 612 V and 600 V/tim from 204 V and 90.7 V/ttm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of r/which present the enhanced ability of interface charge on EI are defined and analysed.     

不同气体环境下532nm激光诱导硅表面形貌的研究

研究了在不同气体环境下,利用532nmNd：YAG纳秒脉冲激光累积辐照单晶硅表面形成的微结构,结果表明,在其他条件相同,背景气体不同的情况下,背景气体对硅表面形貌的形成起着重要的作用。具体分析了真空、N2和SF6 3种环境气氛下形成的微结构,结果显示,在sF6中形成的锥形微结构的数密度比在N2和真空中的大,并且锥形具有更大的纵横比;在N2、真空和sF6中形成的微结构尺寸依次减小。sF6气氛下,激光辅助化学刻蚀的效率比在真空和N2气氛中的高。另外,辐照区域边缘有波纹微结构形成,分析认为,该微结构的形成是由表面张力波的冷却导致的。     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H-SiC P-i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 × 10-5 A/cm2.